1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory devices, particularly to a flash type nonvolatile semiconductor memory device.
2. Description of the Background Art
The flash type nonvolatile semiconductor memory device, i.e., the flash memory, has the capability to electrically write/erase a memory cell at one time. Such a nonvolatile semiconductor memory device is widely used in portable equipment by virtue of its low cost and electrically erasable function.
A flash memory employs, as a memory cell, a transistor including a control gate and a floating gate to allow change of the threshold voltage (referred to as “memory cell transistor” hereinafter).
A gate insulation film is present between the floating gate and the substrate. An insulation film is also present between the floating gate and the control gate. The floating gate is literally in an electrically floating status.
With regards to flash memories, the so-called “NOR type” flash memory is known. This NOR type flash memory is advantageous in that the write speed is high since, in the write operation, writing is effected with, for example, channel hot electrons.
In an erasure operation of the NOR type flash memory, the threshold voltage of the memory cell transistor is driven, for example, from the high level to the low level.
As one method of the erasure operation in such an NOR type flash memory, the so-called “edge draw type” method of drawing electrons in the floating gate to the source region at the time of erasure is known. As another erasure method, the “full channel plane draw type erasure” method that draws electrons to the entire plane of the channel is known. The NOR type flash memory employing the full channel plane draw type erasure method is advantageous in that the memory cell size can be scaled, i.e., reduced, as compared to the conventional edge draw type flash memory.
FIG. 18 is a flow chart showing an example of the simplest erasure sequence in a conventional flash memory.
Referring to FIG. 18, an erasure command is input at step S101. At step S102, an erasure pulse having a predetermined pulse width is applied to the memory cell transistor.
As step S103, the “erasure verification operation” determining whether data has been erased or not is effected. Determination is made of the threshold voltage of the memory cell transistor subjected to erasure pulse application.
When determination is made that the data stored in the memory cell has not been erased as step 103, control returns to step S102. The steps of S102 and S103 are repeated until the threshold voltage of the memory cell transistor becomes lower than a predetermined level of an erasure determined voltage to repeat the erasure pulse application and erasure verification operation.
When determination is made that the threshold voltage of the memory cell transistor is below the erasure determined voltage level, control proceeds to step S104, and the erasure operation ends.
FIG. 19 is a schematic diagram to describe the voltage applied to the memory cell transistor in a memory block according to the conventional first erasure pulse apply method carried out at step S102 of FIG. 18.
For the sake of simplification, the example of FIG. 19 is based on memory cell transistors arranged in 2 rows and 2 columns.
Referring to FIG. 19, the potential levels of a word line WL1 and a word line WL2 provided corresponding to respective rows of memory cells in the memory cell block are fixed to the ground potential in an erasure pulse application mode.
Bit lines BL1 and BL2 provided corresponding to the columns of memory cells in the memory cell block attain an open state during the erasure pulse application. A source line SL to supply a common source potential to the sources of the 2×2 memory cell transistors is applied with a pulse voltage that has, for example, a height of 10V and a width of 10 msec as the erasure pulse.
FIG. 20 is a schematic diagram of a memory block to describe the application of voltage according to the conventional second erasure pulse application method carried out at step S102 of the FIG. 21.
For the sake of simplification, the memory block in FIG. 20 is arranged with memory cell transistors of 2 rows and 2 columns, each having a floating gate. The applied erasure pulse is selected so that a source line potential VSL has an amplitude of, for example, 10V and a time width of 10 msec. Also, a voltage of a pulse with the amplitude of −10V and the time width of 10 msec is applied to all the word lines coupled to the control gates of the memory cell transistors of each row in the block in synchronization with the pulse application to the source line. Bit lines BL1 and BL2 coupled to the drains of the memory cell transistors of each row are all set to an open state.
The above-described pulse application method is employed in the aforementioned “full channel plane draw erasure” type NOR flash memory.
In this case, a pulse voltage similar to that applied to source line SL is applied, not only as source line potential VSL of the transistor, but also as a well potential VWELL of the transistor.
FIG. 21 is a diagram to describe the arrangement of the voltage applied to the memory cell transistor when the erasure pulse described with reference to FIG. 20 is applied.
Referring to FIG. 21, source potential VSL applied to the source of the memory cell transistor and well transistor VWELL applied to the substrate portion of the memory cell transistor are both set to 10V, as described above. Word line potential VWL applied to the word line to select a memory cell transistor is set to −10V. Here, the drain of the memory cell transistor is set to an open state. Therefore, a high electric field is applied between a gate G and a substrate SUB, as well as between gate G and a source S. Thus, electrons are drawn all over the channel plane of the memory cell transistor to effect erasure.
FIG. 22 is a schematic diagram to describe the voltage applied to a memory cell transistor in a conventional third erasure pulse application method carried out at step S102 of FIG. 18.
In the example of FIG. 22, an erasure pulse with the height of −10V and the width of 10 msec is applied to source line SL. Word lines WL1 and WL2 are both applied with an erasure pulse that has, for example, a height of 10V and a width of 10 msec. Here, bit lines BL1 and BL2 are in an open state.
In the case where such an erasure pulse is supplied, an erasure state is attained when the threshold voltage is pulled up from the low level to the high level and exceeds a predetermined level.
FIG. 23 is a diagram to describe the voltage applied to the memory cell transistor in an erasure verification operation carried out at step S103 according to the sequence of FIG. 18. It is assumed that n rows×m columns (n, m: natural number) of memory cell transistors are arranged in the block in FIG. 22.
Referring to FIG. 23, well potential VWELL and source potential VSL are both set to 0V. The potential of a word line WL (i) (1≦i≦n) to select a memory cell transistor corresponding to the selected bit is set to 3.5V. The other word lines are all set to 0V. A bit line BL (j) (1≦j≦m) connected to the memory cell transistor corresponding to the selected bit is set to 1.0V. All the other bit lines are set to 0V. By verifying the current flowing to the memory cell transistor with the above-described potential setting, the threshold voltage or the memory cell transistor can be confirmed. In other words, determination can be made whether erasure of the memory cell transistor has been effected or not.
FIG. 24 shows the voltage applied to the memory cell transistor corresponding to the selected bit of FIG. 23.
Referring to FIG. 24, the source and well of a selected memory cell transistor MT (j, i) are both set to 0V. 3.5V and 1.0V are applied to the gate and drain, respectively, of the memory cell transistor.
The voltage setting in a read mode in a conventional flash memory will be described here. FIG. 25 is a circuit diagram to describe the voltage setting in the read operation of a conventional flash memory.
Referring to FIG. 25, a word line WL (i) connected to the gate of the memory cell transistor corresponding to the selected bit is set to, for example, 4.5V. All the other word lines are set to 0V. Here, source line potential VSL and well potential VWELL are both set to 0V.
FIG. 26 shows the potential applied to the memory cell transistor selected in a read mode of FIG. 25.
Referring to FIG. 26, the source and well of the memory cell transistor corresponding to the selected bit are both set to 0V. 1.0V is applied to the drain and 4.5V is applied to the gate. When the threshold voltage of the memory cell transistor is high, no current flows from the drain to source. In contrast, when the threshold voltage of the memory cell transistor is low, current flows from the drain to the source. Therefore, determination can be made whether data is written into the memory cell transistor by detecting this current flow.
In a conventional NOR type flash memory, the erasure operation is carried out in block units of memory cells. An erasure pulse voltage is applied at one time to a plurality of memory cell transistors in the block.
It is to be noted that the electrical characteristic of each memory cell transistor is essentially variable. Therefore, variation will be exhibited in the threshold voltage of each memory cell after the erasure pulse is applied in the above-described one-time pulse application. There was a problem that it is difficult to set uniform the threshold voltage of each memory cell transistor.
When the variation in the threshold voltage is great, memory cells of the so-called “excessively erased” state will be present in the memory cell block. In the case where the threshold voltage is to be driven from a high level to a low level in an erasure operation in a memory cell block with such excessively-erased memory cells, the memory cell transistor of the excessively-erased state will become a depletion transistor. This means that much leakage current will flow when the gate voltage is 0V, i.e., even when the memory cell transistor is in a non-selected state.
The presence of such excessively-erased memory cell transistors will cause a great amount of leakage current to flow due to the excessively-erased memory cell transistors that are not selected on the same bit line when in, for example, an erasure verification operation. There is a problem that the value of the current flowing to the relevant memory cell transistor that is selected by the sum of the leakage current can no longer be identified. In other words, it was difficult to carry out an accurate verification operation. Furthermore, in some cases, it was difficult to carry out a read operation.